1. Field of the Invention
The present invention relates to a cache memory connected between a central processing unit (CPU) executing high speed computing processing and a main memory effecting a relatively low speed operation in a computer. More particularly, it relates to a cache memory which processes instruction data from the main memory and thus can realize high speed decoding of the instruction data in the CPU.
2. Description of the Related Art
Recently, CPUs which execute a greater part of an instruction in one cycle have been developed. Nevertheless, they are required to execute high speed processing. To this end, cache memories provided for the respective CPUs are also required to effect high speed operation accordingly.
As one approach to realizing high speed computing processing, an idea of increasing a frequency of the operational clock has been proposed. This, however, is difficult to realize because a peripheral circuit, for example, constituted by transistor-transistor logic (TTL), cannot satisfactorily meet conditions required for the operational clock frequency. Accordingly, other approaches to realizing high speed processing without increasing the frequency of the operational clock have been demanded.
As an approach to meet the demand, a technique of simultaneously executing a plurality of instructions is known, which is roughly classified into two categories. One is the case that each instruction has a fixed length, and the other is the case that each instruction has a variable length. With respect to a data processor which processes a plurality of fixed length instructions, a position of a next instruction succeeding an instruction is fixed and, accordingly, it is possible to simultaneously execute the two neighboring instructions.
However, with respect to a data processor which processes a plurality of variable length instructions as is described in The Real Time Operating System Nucleus (TRON) Specification Chip Architecture Overview, a problem is posed. Namely, since the position of the succeeding instruction is changed or not fixed, it is impossible to simultaneously execute the two neighboring instructions so long as the position of the succeeding instruction is not specified by any means.
Thus, in a prior art data processor processing variable length instructions as in the TRON Specification, a problem occurs in that it is impossible to simultaneously execute a plurality of instructions and thus realize a high speed computing processing. In other words, to realize high speed processing, a cache memory connected between a CPU and a main memory must be improved with respect to the processing of instruction data from the main memory. To cope with this, various approaches are proposed; however, a known effective improvement has not been proposed.
The problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.